The present invention pertains to systems and methods for simultaneously producing a diffusion barrier and a seed layer used in integrated circuit metallization. This is achieved by initially depositing copper-magnesium (Cuxe2x80x94Mg) alloys with relatively high levels of Mg ( greater than 10 atomic %, which is equivalent to about  greater than 4 weight %). After the alloys are deposited, they self-form a magnesium oxide (MgO) based barrier layer at the substrate interface, thus eliminating the need for a separate operation for barrier deposition. The migration of Mg to the substrate interface leaves the remainder of the film relatively pure Cu.
Integrated circuit (IC) manufacturers have traditionally used aluminum, among other metals, as the conductive metal for interconnects in integrated circuits. While copper has a higher conductivity and greater electromigration resistance than aluminum, it has not been used in the past because of certain challenges it presents. For example, the adhesion of Cu to silicon dioxide (SiO2) and to other dielectric materials is generally poor due to the low enthalpy of formation of the associated Cu compounds. Also, Cu ions readily diffuse into SiO2 under electrical bias and increases the dielectric electrical leakage between lines even at very low Cu concentrations. In addition, if copper diffuses into the underlying silicon where the active devices are located, device performance can be degraded. Copper behaves as a defect in silicon resulting in the reduction of minority carrier lifetime, and hence, device degradation. Furthermore, Cu will also react with silicon at relatively low temperature to form copper silicides that increase contact resistance.
Recently, IC manufacturers have been turning to copper because of the development of Damascene processing that enables Cu interconnect metallization. Damascene processing involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (intermetal dielectric=IMD). However, the problem of the high diffusivity of copper in silicon dioxide (SiO2) and in other IMDs remains of great concern.
To deal with this issue, an integrated circuit substrate must be coated with a suitable barrier layer that blocks diffusion of copper atoms. It is typically formed over the dielectric layer and prior to deposition of copper. The time, materials, and process complexity required to form a separate diffusion barrier layer introduces a significant cost to the overall fabrication procedure. Also, if the barrier is too thick, it can create problems with subsequent Cu coating and filling of ultra-fine featuresxe2x80x94e.g., a sub-0.1 xcexcm diameter via.
The International Technology Roadmap for Semiconductors (ITRS 1999) states that barrier film thickness should be no thicker than 100 xc3x85 at the 0.10 xcexcm technology node, and preferably as thin as possible. Cuxe2x80x94Mg alloys are one possible solution for forming diffusion barriers which meet this need and, using the methods disclosed herein, can be extended to future technology nodes as well. Cuxe2x80x94Mg alloys effectively promote adhesion to the intermetal dielectric and have a much lower resistivity compared to conventional diffusion barriers such as tantalum and tantalum nitride (tens of xcexcxcexa9-cm versus hundreds of xcexcxcexa9-cm). Possible procedures for forming Cuxe2x80x94Mg alloys of low Mg concentration ( less than  less than 10 atomic %, typically about 1 atomic %, or 1 at. %) involve self-forming MgO barriers by Mg migration. With integrated circuits allowing large feature sizes, such low Mg concentration alloys could have been used because a thick alloy would contain enough Mg atoms to produce the desired MgO layer. However, feature sizes in ICs have already decreased to the point where the barrier thickness is limited to less than about 200 xc3x85. Hence, the Cuxe2x80x94Mg alloy that is less than 200 xc3x85 needs to contain high percentage of Mg (greater than 10 atomic %) to form a robust MgO barrier. The relationship between the minimum Mg content in the alloy and the maximum allowable Cuxe2x80x94Mg thickness will be presented in the body of this patent.
High Mg content Cuxe2x80x94Mg alloys have several associated problems. For example, Mg like many other dopants, greatly increases the resistivity of copper for any excess Mg, i.e., unreacted Mg, that stays within the alloy layer. The increased resistivity tends to negate the advantage offered by low-resistivity Cuxe2x80x94Mg alloys that can act as a seed layer for subsequent electrochemical deposition of copper. Excess Mg can also migrate to the exposed surface of the alloy layer, thus forming a MgO layer upon exposure to air that can interfere with the Cu electroplating step. The unreacted Mg may also diffuse out of the seed layer and into adjacent Cu interconnects and vias, increasing the Cu resistivity in those areas to unacceptable levels ( greater than 2.0 xcexcxcexa9-cm).
What is therefore needed is a process for forming a single layer out of high Mg-content Cuxe2x80x94Mg alloys that obviates these and other problems, and simultaneously serves as a robust barrier to Cu diffusion and conductive seed layer for subsequent operations. In conventional IC nomenclature, the diffusion barrier and the seed layer are two separate films. Since this invention contemplates the use of a single metallic film for both applications, it is important to note that the alloy layer provides for the formation of an interfacial diffusion barrier (interfacial meaning the interface between the dielectric and the metallization layer) whereas the remainder of the alloy serves as the seed layer. In other words, the Cuxe2x80x94Mg alloy layer is equivalent to the barrier film according to conventional nomenclature even though in the case of Cuxe2x80x94Mg alloy films, the interfacial diffusion barrier is much thinner than the overall alloy layer thickness.
The present invention pertains to systems and methods for simultaneously producing a diffusion barrier and a seed layer used in integrated circuit metallization. This is achieved by initially depositing copper-magnesium (Cuxe2x80x94Mg) alloys with relatively high levels of Mg ( greater than 10 atomic %, which is equivalent to about  greater than 4 weight %). After the alloys are deposited, they self-form a magnesium oxide (MgO) based barrier layer at the substrate interface, thus eliminating the need for a separate operation for barrier deposition. The migration of Mg to the substrate interface leaves the remainder of the film relatively pure Cu. The amount of Mg is calculated to provide a continuous layer of MgO barrier. Thus, one should control the absolute amount of magnesiumxe2x80x94rather than a percentage concentration of magnesiumxe2x80x94in the alloy layer. The deposition and annealing conditions are controlled so that most of the Mg migrates to the dielectric to form the MgO, leaving little Mg in the bulk of the copper alloy or at the exposed alloy surface.
One aspect of the invention provides for a method of forming, from a single copper alloy layer, a self-forming diffusion barrier layer and a copper seed layer. The method includes depositing the single copper alloy layer on a dielectric material wherein the single copper alloy layer contains at least 10 atomic percent magnesium and whereby the single copper alloy layer can react with the dielectric material and self-form a diffusion barrier layer at the interface between the single copper alloy layer and the dielectric material. Another aspect of the invention provides for a method of forming, from a single copper alloy layer, a self-forming diffusion barrier layer and a copper seed layer. The method includes depositing the single copper alloy layer on a dielectric material wherein the single copper alloy layer contains another metal and whereby the single copper alloy layer can react with the dielectric material and self-form a diffusion barrier layer at the interface between the single copper alloy layer and the dielectric material, and wherein the other metal is boron, tantalum, aluminum, titanium, or beryllium.
Both of these methods can include a dielectric material that is oxide-based or polymer-based. In the magnesium aspect, the self-forming barrier layer can be magnesium oxide or magnesium silicon oxide. The single copper alloy layer can be deposited by using a cathode target with separate copper and magnesium sections, and using a hollow-cathode magnetron. The single copper alloy layer can be less than about 1500 xc3x85 thick and the diffusion barrier layer greater than 10 xc3x85 thick. An annealing operation can be implemented for about 50 to 500 seconds and where the temperature is between about 50 to 500xc2x0 C. Part or all annealing operation can be carried out under vacuum. After deposition of the single copper alloy layer, additional copper can be deposited. The methods can be carried out as part of integrated circuit process such as Damascene processing.
Another aspect of the invention provides for an integrated circuit or partially fabricated integrated circuit that includes a dielectric material and a single copper alloy layer on the dielectric material, wherein the single copper alloy layer contains at least 10 atomic percent magnesium. The circuit can include a dielectric material that is oxide-based or polymer-based. The single copper alloy layer can be deposited by using a cathode target with separate copper and magnesium sections, and using a hollow-cathode magnetron. The single copper alloy layer can be less than about 1500 xc3x85 thick and the diffusion barrier layer can be greater than 10 xc3x85 thick. An annealing operation can be implemented for about 5 to 500 seconds and where the temperature is between about 50 to 500xc2x0 C. The circuit can be fabricated as part of integrated circuit process such as Damascene processing.
Another aspect of the invention provides for a method of forming, from a single layer, a self-forming barrier layer. The method includes depositing the single layer on a dielectric material wherein the single layer contains about 100 atomic percent magnesium and whereby the single layer can react with the dielectric material and self-form a barrier layer at the interface between the single layer and the dielectric material. Another aspect of the invention provides for a method of forming, from a single layer, a self-forming barrier layer. The method includes depositing the single layer on a dielectric material wherein the single layer contains a metal whereby the single layer can react with the dielectric material and self-form a barrier layer at the interface between the single layer and the dielectric material, and wherein the other metal is boron, tantalum, aluminum, titanium, or beryllium.
Both of these methods can include a dielectric material that is oxide-based or polymer-based. In the magnesium aspect, the self-forming barrier layer can be magnesium oxide or magnesium silicon oxide. The single copper alloy layer can be less than about 1500 xc3x85 thick and the barrier layer greater than 10 xc3x85 thick. An annealing operation can be implemented for about 5 to 500 seconds and where the temperature is between about 50 to 500xc2x0 C. The methods can be carried out as part of integrated circuit process such as Damascene processing.
Another aspect of the invention provides for an integrated circuit or partially fabricated integrated circuit that includes a dielectric material and a single layer on the dielectric material, wherein the single layer contains about 100 atomic percent magnesium. The barrier layer can be greater than about 10 xc3x85 thick. An annealing operation can be implemented for about 5 to 500 seconds and where the temperature is between about 50 to 500xc2x0 C. The circuit can be fabricated as part of integrated circuit process such as Damascene processing.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.